Sunday, June 19, 2011

Semiconductor Development from the First Transistor to 3D-Chip

The first transistor was invented at Bell Laboratories on December 16, 1947 by William Shockley. It replaced Vacuum tubes in the years after gradually, and Radio was marked on the case as Solid State to interpret the durability of Transistor. Shock in a much high order than vacuum tubes, on the other hand it operates in less power and energy than the vacuum tube, and It is pretty SMALL.
In 1959 both TI and Fairchild parties applied for patents of IC. Jack Kilby and Texas Instruments received U.S. patent #3,138,743 for miniaturized electronic circuits. Robert Noyce and the Fairchild Semiconductor Corporation received U.S. patent #2,981,877 for a silicon based integrated circuit. The two companies wisely decided to cross license their technologies after several years of legal battles, creating a global market now worth about $1 trillion a year.
In 1961 the first commercially available IC came from the Fairchild Semiconductor Corporation. All computers then started to be made using chips instead of the individual transistors and their accompanying parts. Texas Instruments first used the chips in Air Force computers and the Minuteman Missile in 1962. The original IC had only one transistor, three resistors and one capacitor and was the size of an adult's pinkie. They used the chips to produce the first electronic portable calculators later.
The first integrated circuits contained only a few transistors. Called "small-scale integration" (SSI), Early linear ICs such as Plessey SL201 or Philips TAA320 had as few as two transistors. The term Large Scale Integration was first used by IBM scientist Rolf Landauer when describing the theoretical concept, from there came the terms for SSI, MSI, VLSI, and ULSI.
SSI circuits were crucial to early aerospace projects, and vice-versa. Both the Minuteman missile and Apollo program needed lightweight digital computers for their inertial guidance systems. The Minuteman missile program and various other Navy programs accounted for the total $4 million integrated circuit market in 1962, and by 1968, U.S. Government space and defense spending still accounted for 37% of the $312 million total production. The demand by the U.S. Government supported the nascent integrated circuit market until costs fell enough to allow firms to penetrate the industrial and eventually the consumer markets. The average price per integrated circuit dropped from $50.00 in 1962 to $2.33 in 1968. Integrated circuits began to appear in consumer products by the turn of the decade, a typical application being FM inter-carrier sound processing in television receivers.
In the late 1960s, introduced devices which contained hundreds of transistors on each chip, called "medium-scale integration" (MSI).
They were attractive economically because while they cost little more to produce than SSI devices.
Later, driven by the same economic factors, led to "large-scale integration" (LSI) in the mid 1970s, with tens of thousands of transistors per chip.
Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that began to be manufactured in moderate quantities in the early 1970s, had under 4,000 transistors. True LSI circuits, approaching 10,000 transistors, began to be produced around 1974, for computer main memories and second-generation microprocessors.
Remember your Texas Instrument Programmable Calculator when you was in the University in the 70’s.
VLSI Very-large-scale integration IC
Upper interconnect layers on an Intel 80486DX2 microprocessor. The final step in the development process, starting in the 1980s and continuing through the present, was "very large-scale integration" (VLSI). The development started with hundreds of thousands of transistors in the early 1980s, and continues beyond several billion transistors as of 2009.
Multiple developments were required to achieve this increased density. Manufacturers moved to smaller rules and cleaner fabrication, through the use of advance semiconductor equipment. They could make chips with more transistors and maintain adequate yield. The path of process improvements was summarized by the International Technology Roadmap for Semiconductors (ITRS). Design tools improved enough to make it practical to finish these designs in a reasonable time. The more energy efficient CMOS replaced NMOS and PMOS, avoiding a prohibitive increase in power consumption.
In 1986 the first one megabit RAM chips were introduced, which contained more than one million transistors. Microprocessor chips passed the million transistor mark in 1989 and the billion transistor mark in 2005. The trend continues largely unabated, with chips introduced in 2007 containing tens of billions of memory transistors.
To reflect further growth of the complexity, the term ULSI that stands for "ultra-large-scale integration" was proposed for chips of complexity of more than 1 million transistors.
Wafer-scale integration (WSI) is a system of building very-large integrated circuits that uses an entire silicon wafer to produce few single "super-chip". Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers. The name is taken from the term Very-Large-Scale Integration, the current state of the art when WSI was being developed.
A system-on-a-chip (SoC or SOC) is an integrated circuit in which all the components needed for a computer or other systems are included on a single chip. The design of such a device can be complex and costly, and building disparate components on a single piece of silicon may compromise the efficiency of some elements. However, these drawbacks are offset by lower manufacturing and assembly costs and by a greatly reduced power budget: because signals among the components are kept on-die, much less power is required.
POP is package on package that is to stack the package on top of another package. The target is to increase the function and minimize the chip size both x and y.
On Packaging side, memory Chip is the competitive technology that is to stack up many as 10 chips on top the other on both side of the substrates, whereby, tiny gold wire of diameter 0.008 inch are used to interconnect the chips to the lead of the outer package by using the speed of 20 wires per second provided by the world fastest Gold ball bonder supplied by the major equipment supplier ASM and K & S. and the total package is only 1mm thick. This results that we can have an USB memory stick that can have 32G memory.
While more chips are built on a single chip and is operation in Giga operations in a second, technology is how to do Chip cooling down, the material, the thermal management, and the selection of the substrate matching the chip as not to crack the chip due to temperature rising and mechanical expansion. H how to apply the state of the Art o Cooling system by Air, Fins and Fans, water embedded porous copper material for efficient cooling such as Metaform. When we do Google , the Google server and network will operate and generate certain Kilo of CO2 in the world. As the microprocessor operate and that generate heat, so some one has proposed to install the server in the Polar area.
3D chips are expected to solve a number of problems for chipmakers who are aiming for performance increases in ever-smaller chips. As transistor density rises, the wires connecting them have become both thinner and closer together, resulting in increased resistance and overheating. And that leads to the demand of super accurate Gold ball bonder that connect thousand wires inside the chip here to there. These problems cause signal delays, packaging concern for the chip, limiting the clock speed of central processing units.
A three-dimensional integrated circuit (3D-IC) has two or more layers of active electronic components that are integrated both vertically and horizontally into a single circuit. Communication between layers uses on-die signaling, so power consumption is much lower than in equivalent separate circuits. Judicious use of short vertical wires can substantially reduce overall wire length for faster operation.
Taiwan Semiconductor Manufacturing Co. is vying with Intel to become the first company to sell three-dimensional chips that boost the density of transistors in a single semiconductor by up to 1,000 times.
TSMC, the world's largest contract chipmaker in the world, could make its first 3D chips commercially available before the end of 2011, according to a person close to the situation who requested anonymity.
The timeframe for TSMC matches the end-2011 schedule that Intel has set for the launch of its 3D Tri-Gate chips, which the company expects to be the world's first commercial 3D chip and the most significant advance in chip technology since the development of the chip transistor in the 1948.
With several layers of silicon stacked together, a 3D chip can achieve performance gains of about a third while consuming 50 percent less power. For this reason, 3D chips are particularly well suited to power new generations of mobile devices such as tablets and mobile phones, and to offer more operative hours from the battery cell. Businesses where Intel has so far failed to establish a significant presence.
3D chips look more attractive because of their greater density, it is more difficult to make them because of the testing issues. If you have five stacked dies and one of the dies is bad, you have to scrap the whole thing. The Yield is a challenge!
TSMC is developing so-called 2D chips that replace an organic polymer substrate with silicon to boost transistor density. Communications chipmaker Xilinx has contracted TSMC to make its Virtex-7 field programmable gate array (FPGA) using TSMC's 2D chip technology that puts three chip dies on one silicon substrate. Xilinx said on March 8 that it expects the first samples of the Virtex-7 485T FPGA to be available by August.
TSMC has been working closely with chip packagers and providers of design automation software to help commercialize 3D chip technology.
In April 2007, IBM and Rensselaer Polytechnic Institute (RPI) researchers announced the first versions of 3D chips with support from the Defense Advanced Research Project Agency (DARPA). The 3D chips combined several layers of silicon using a technique called wafer bonding.
IBM's technique used a silicon base with active wafers layered on top. This technology allowed a processor to be placed on the bottom of the stack with memory or other components layered across the top, resulting in a thousand-fold reduction in connector length. The greater transistor density reduced the distance data has to travel, reducing processing time.
IBM used through-silicon vias (TSVs) to connect stacks of multiple chip components. TSVs allow for more efficient heat dissipation through the stack to cooling systems that improve power efficiency.

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